defines a high-speed, low-latency, two-wire serial interface that connects a System-on-Chip (SoC) processor to one or more Power Management Integrated Circuits (PMICs). Its primary role is to accurately monitor and dynamically control supply voltages in real time based on the processor's current workload. In technical terms: The Master: Resides within the SoC's integrated Power Controller (PC). The Slave: Resides within the PMIC's voltage regulation systems. Key Technical Features
The full is available exclusively to MIPI Alliance members . mipi spmi specification pdf
Understanding the MIPI SPMI Specification: A Comprehensive Guide to System Power Management The Slave: Resides within the PMIC's voltage regulation
SPMI supports prioritised data transmission through its traffic‑class mechanism. Critical power‑management commands—such as a voltage‑scaling instruction needed to prevent an impending brownout—can be assigned a higher priority than less urgent traffic, ensuring they are serviced promptly. defines a high-speed
algorithm for masters and priority-based management (A-bit/SR-bit) for request-capable slaves to resolve bus contention. Command Set : Supports specialized power management commands such as Reset, Sleep, Shutdown, Wakeup , and Authenticate. Data Integrity : Includes odd parity for error detection and
Allows slave devices (like PMICs) to initiate communication and request arbitration, facilitating more responsive power management.
If you can tell me if you are looking for a (like 1.0, 2.0, or 3.0) or want to know about implementing SPMI in a specific application , I can provide more tailored information. System Power Management - MIPI SPMI - MIPI.org